The In-Target Probe (ITP) run-time control tool is used to test functional silicon devices. More specifically, the ITP tool provides examination and manipulation of an architectural state, system memory access, software debugging, chipset resource access, as well as root-cause platform routing and signal integrity evaluations. The ITP tool suite may provide such analysis by attempting to manually correlate a logic state either from a post-failure analysis of stored data from internal registers, memories and Joint Test Access Group (JTAG) scan elements, or by inferring from an execution state as observed from a front-side address, data and control bus. The foregoing approach often does not provide suitable and/or efficient observation of events within a target device, particularly within the debug time span.
A logic analyzer may be coupled to the ITP tool in order to improve the quality of an integrated hardware and software test. The logic analyzer may present all data that is transmitted over the front-side bus during operation of the device. Such an approach is prohibitively expensive for almost all envisioned usage scenarios. Moreover, this approach is often unsuitably inefficient due to the large ratio of presented data to relevant data. Other testing approaches include emitting specific data onto the front side bus using special transactions, writing data to special memory locations for post-test extraction, or writing data to a byte location on the device known as “port 80”.
The complexity of target devices continues to increase despite the foregoing limitations in testing systems. The increased complexity may be manifested in many ways, including but not limited to an increased number of processing units one die and a reduction of meaningful coherency between internal execution data and front side bus data. The increasing complexity of target devices and limitations in conventional testing systems present difficult challenges to the low-level software developer.